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30 lines
571 B
Verilog
30 lines
571 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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module t (/*AUTOARG*/);
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integer i;
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integer a_var;
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sub sub ();
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initial begin
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nf = 0; // z not found
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sub.subsubz.inss = 0; // subsub not found
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i = nofunc(); // nofunc not found
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notask(); // notask not found
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a_var(); // Calling variable as task
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$finish;
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end
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endmodule
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module sub;
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subsub subsub ();
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endmodule
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module subsub;
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integer inss;
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endmodule
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