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33 lines
1.5 KiB
Verilog
33 lines
1.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t;
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reg signed [20:0] longp; initial longp = 21'shbbccc;
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reg signed [20:0] longn; initial longn = 21'shbbccc; initial longn[20]=1'b1;
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reg signed [40:0] quadp; initial quadp = 41'sh1_bbbb_cccc;
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reg signed [40:0] quadn; initial quadn = 41'sh1_bbbb_cccc; initial quadn[40]=1'b1;
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reg signed [80:0] widep; initial widep = 81'shbc_1234_5678_1234_5678;
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reg signed [80:0] widen; initial widen = 81'shbc_1234_5678_1234_5678; initial widen[40]=1'b1;
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initial begin
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// Display formatting
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$display("[%0t] lp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
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longp, longp, longp, longp, longp, longp);
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$display("[%0t] ln %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
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longn, longn, longn, longn, longn, longn);
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$display("[%0t] qp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
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quadp, quadp, quadp, quadp, quadp, quadp);
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$display("[%0t] qn %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
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quadn, quadn, quadn, quadn, quadn, quadn);
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$display("[%0t] wp %%x=%x %%x=%x %%o=%o %%b=%b", $time,
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widep, widep, widep, widep);
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$display("[%0t] wn %%x=%x %%x=%x %%o=%o %%b=%b", $time,
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widen, widen, widen, widen);
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$display;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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