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23 lines
547 B
Systemverilog
23 lines
547 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(y, y2);
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output [3:0] y;
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output [31:0] y2;
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// bug775
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// verilator lint_off WIDTH
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assign y = ((0/0) ? 1 : 2) % 0;
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// bug2460
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reg [31:0] b;
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assign y2 = $signed(32'h80000000) / $signed(b);
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initial begin
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b = 32'hffffffff;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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