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The end iterator always points to an element past the end of the list. When new elements are added to the back of the list, they are inserted before the end iterator. Instead, track the last element in the list at the start of processing and stop after it's been processed.
30 lines
579 B
Systemverilog
30 lines
579 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 Wilson Snyder and Marlon James.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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input clk
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);
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reg [31:0] count /*verilator public_flat_rd */;
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// Test loop
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initial begin
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count = 0;
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end
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always @(posedge clk) begin
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count <= count + 2;
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if (count == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule : t
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