mirror of
https://github.com/verilator/verilator.git
synced 2025-01-07 15:17:36 +00:00
599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
48 lines
1.1 KiB
Systemverilog
48 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// Copyright 2022 by Geza Lore. This program is free software; you can
|
|
// redistribute it and/or modify it under the terms of either the GNU
|
|
// Lesser General Public License Version 3 or the Perl Artistic License
|
|
// Version 2.0.
|
|
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
|
|
|
`ifdef VERILATOR
|
|
// The '$c1(1)' is there to prevent inlining of the signal by V3Gate
|
|
`define IMPURE_ONE $c(1);
|
|
`else
|
|
// Use standard $random (chaces of getting 2 consecutive zeroes is zero).
|
|
`define IMPURE_ONE |($random | $random);
|
|
`endif
|
|
|
|
module top(
|
|
clk
|
|
);
|
|
|
|
input clk;
|
|
|
|
reg clk_half = 0;
|
|
|
|
reg [31:0] cyc = 0;
|
|
reg [31:0] a, b, c;
|
|
|
|
always @(posedge clk) begin
|
|
$display("tick %d: a: %d, b: %d, c: %d", cyc, a, b, c);
|
|
// Check invariant
|
|
if (a !== cyc + 1) $stop;
|
|
if (b !== cyc + 2) $stop;
|
|
if (c !== cyc + 2) $stop;
|
|
// End of test
|
|
if (cyc == 100) begin
|
|
$write("*-* All Finished *-*\n");
|
|
$finish;
|
|
end
|
|
|
|
cyc <= cyc + 1;
|
|
end
|
|
|
|
always @(a) b = a + `IMPURE_ONE;
|
|
always @(cyc) a = cyc + `IMPURE_ONE;
|
|
assign c = a + `IMPURE_ONE;
|
|
|
|
endmodule
|