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24 lines
416 B
Systemverilog
24 lines
416 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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extern program pgm;
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program pgm;
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task ptask;
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endtask
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endprogram
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module t(/*AUTOARG*/);
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pgm sub ();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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