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23 lines
437 B
Systemverilog
23 lines
437 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input wire clk,
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input wire [7:0] i,
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input wire a,
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output reg [7:0] o
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);
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reg cond = 0;
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always @(posedge clk) begin
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if (cond) o = i;
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cond = a;
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if (cond) o = ~i;
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end
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endmodule
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