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28 lines
658 B
Systemverilog
28 lines
658 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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function automatic int recurse_1;
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input int i;
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if (i == 0) recurse_1 = 0;
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else recurse_1 = i + recurse_2(i);
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endfunction
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function automatic int recurse_2;
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input int i;
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return recurse_1(i - 1) * 2;
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endfunction
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initial begin
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if (recurse_1(0) != 0) $stop;
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if (recurse_1(3) != (3 + 2*(2 + 2*(1)))) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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