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97 lines
2.3 KiB
Systemverilog
97 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Test for using DPI as general accessors
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012.
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// SPDX-License-Identifier: CC0-1.0
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//
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// Contributed by Jeremy Bennett and Jie Xul
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//
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// This test exercises the use of DPI to access signals and registers in a
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// module hierarchy in a uniform fashion. See the discussion at
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//
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// https://github.com/verilator/verilator/issues/1750
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//
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// We need to test read and write access to:
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// - scalars
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// - vectors
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// - array elements
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// - slices of vectors or array elements
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//
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// We need to test that writing to non-writable elements generates an error.
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//
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// This Verilog would run forever. It will be stopped externally by the C++
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// instantiating program.
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// Define the width of registers and size of memory we use
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`define REG_WIDTH 8
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`define MEM_SIZE 256
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// Top module defines the accessors and instantiates a sub-module with
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// substantive content.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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`include "t_dpi_accessors_macros_inc.vh"
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`include "t_dpi_accessors_inc.vh"
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// Put the serious stuff in a sub-module, so we can check hierarchical
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// access works OK.
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test_sub i_test_sub (.clk (clk));
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endmodule // t
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// A sub-module with all sorts of goodies we would like to access
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module test_sub (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer i; // General counter
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// Elements we would like to access from outside
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reg a;
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reg [`REG_WIDTH - 1:0] b;
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reg [`REG_WIDTH - 1:0] mem [`MEM_SIZE - 1:0];
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wire c;
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wire [`REG_WIDTH - 1:0] d;
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reg [`REG_WIDTH - 1:0] e;
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reg [`REG_WIDTH - 1:0] f;
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// Drive our wires from our registers
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assign c = ~a;
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assign d = ~b;
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// Initial values for registers and array
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initial begin
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a = 0;
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b = `REG_WIDTH'h0;
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for (i = 0; i < `MEM_SIZE; i++) begin
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mem[i] = i [`REG_WIDTH - 1:0];
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end
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e = 0;
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f = 0;
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end
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// Wipe out one memory cell in turn on the positive clock edge, restoring
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// the previous element. We toggle the wipeout value.
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always @(posedge clk) begin
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mem[b] <= {`REG_WIDTH {a}};
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mem[b - 1] <= b - 1;
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a <= ~a;
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b <= b + 1;
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end
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endmodule // test_sub
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