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In order to avoid unexpected breakage on multi-driven variables, we resolve in DFG construction by using only the first driver encountered. Also issues the MULTIDRIVEN error for these signals.
24 lines
559 B
Systemverilog
24 lines
559 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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`default_nettype none
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module t(
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input wire [10:0] i,
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output wire [10:0] o
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);
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logic [10:0] a;
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assign a[3:0] = i[3:0];
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assign a[4:1] = ~i[4:1];
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assign a[3] = ~i[3];
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assign a[8:5] = i[8:5];
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assign a[7:6] = ~i[7:6];
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assign a[9] = i[9];
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assign a[9] = ~i[9];
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assign a[10] = i[10];
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assign o = a;
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endmodule
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