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66 lines
2.0 KiB
Systemverilog
66 lines
2.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off LATCH
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module t_case_huge_sub4 (/*AUTOARG*/
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// Outputs
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outq,
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// Inputs
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index
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);
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input [7:0] index;
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output [9:0] outq;
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// =============================
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg [9:0] outq;
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// End of automatics
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// =============================
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always @(/*AS*/index) begin
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case (index)
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// default below: no change
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8'h00: begin outq = 10'h001; end
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8'he0: begin outq = 10'h05b; end
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8'he1: begin outq = 10'h126; end
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8'he2: begin outq = 10'h369; end
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8'he3: begin outq = 10'h291; end
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8'he4: begin outq = 10'h2ca; end
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8'he5: begin outq = 10'h25b; end
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8'he6: begin outq = 10'h106; end
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8'he7: begin outq = 10'h172; end
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8'he8: begin outq = 10'h2f7; end
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8'he9: begin outq = 10'h2d3; end
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8'hea: begin outq = 10'h182; end
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8'heb: begin outq = 10'h327; end
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8'hec: begin outq = 10'h1d0; end
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8'hed: begin outq = 10'h204; end
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8'hee: begin outq = 10'h11f; end
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8'hef: begin outq = 10'h365; end
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8'hf0: begin outq = 10'h2c2; end
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8'hf1: begin outq = 10'h2b5; end
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8'hf2: begin outq = 10'h1f8; end
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8'hf3: begin outq = 10'h2a7; end
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8'hf4: begin outq = 10'h1be; end
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8'hf5: begin outq = 10'h25e; end
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8'hf6: begin outq = 10'h032; end
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8'hf7: begin outq = 10'h2ef; end
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8'hf8: begin outq = 10'h02f; end
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8'hf9: begin outq = 10'h201; end
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8'hfa: begin outq = 10'h054; end
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8'hfb: begin outq = 10'h013; end
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8'hfc: begin outq = 10'h249; end
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8'hfd: begin outq = 10'h09a; end
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8'hfe: begin outq = 10'h012; end
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8'hff: begin outq = 10'h114; end
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default: ; // No change
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endcase
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end
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endmodule
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