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43 lines
889 B
Systemverilog
43 lines
889 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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int q[$];
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int r;
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function void set_val(ref int lhs, input int rhs);
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lhs = rhs;
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endfunction
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initial begin
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q = { 60, 50, 40 };
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set_val(q[$-1], 30);
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q[$-2] = 20;
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r = q[$];
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if (r != 40) $stop;
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r = q[$-1];
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if (r != 30) $stop;
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q = q[0:$-1]; // void'(q.pop_back()) or q.delete(q.size-1)
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if (q.size != 2) $stop;
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if (q[0] != 20) $stop;
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if (q[1] != 30) $stop;
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q = { 20, 30, 40 };
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q = q[$-1:$];
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if (q.size != 2) $stop;
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if (q[0] != 30) $stop;
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if (q[1] != 40) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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