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33 lines
1.1 KiB
Python
Executable File
33 lines
1.1 KiB
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt_all', 'xsim')
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test.top_filename = "t/t_lib_prot.v"
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if test.benchmark:
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test.sim_time = test.benchmark * 100
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trace_opt = ("" if re.search(r'--no-trace', ' '.join(test.driver_verilator_flags)) else "-trace")
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# Tests the same code as t_lib_prot.py but without --protect-lib
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test.compile(verilator_flags2=['--no-timing', trace_opt, "t/t_lib_prot_secret.v"],
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xsim_flags2=["t/t_lib_prot_secret.v"])
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test.execute()
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if test.vlt and test.trace:
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# We can see the ports of the secret module
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test.file_grep(test.trace_filename, r'accum_in')
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# and we can see what's inside (because we didn't use --protect-lib)
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test.file_grep(test.trace_filename, r'secret_')
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test.passes()
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