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0547108e3f
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com> Signed-off-by: Ryszard Rozak <rrozak@antmicro.com> Signed-off-by: Arkadiusz Kozdra <akozdra@antmicro.com> Co-authored-by: Mariusz Glebocki <mglebocki@antmicro.com> Co-authored-by: Arkadiusz Kozdra <akozdra@antmicro.com> Co-authored-by: Bartłomiej Chmiel <bachm44@gmail.com> Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org> Co-authored-by: Ryszard Rozak <rrozak@antmicro.com>
19 lines
560 B
Python
Executable File
19 lines
560 B
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.lint(verilator_flags2=['--output-groups -1'],
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fails=True,
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expect_filename=test.golden_filename)
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test.passes()
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