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91c8866ac3
Signed-off-by: Arkadiusz Kozdra <akozdra@antmicro.com> Co-authored-by: Szymon Gizler <sgizler@internships.antmicro.com>
32 lines
967 B
Systemverilog
32 lines
967 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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typedef enum {efgh} en;
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module t (/*AUTOARG*/);
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initial begin
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en e;
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string s;
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s = {"a", "b"};
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if (s != "ab") $stop;
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e = efgh;
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s = {"abcd", e.name(), "ijkl"};
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if (s != "abcdefghijkl") $stop;
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// hang V3Width if complexity grows exponential (2**52 should suffice)
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s = {"a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m",
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"n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z",
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"a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m",
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"n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z"};
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if (s != "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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