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16 lines
303 B
Systemverilog
16 lines
303 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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typedef logic [3:0] foo_t;
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foo_t foo_s;
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assign bar_s = {foo_s, foo_s}.f1;
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endmodule
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