verilator/test_regress/t/t_param_default_bad.v
2020-03-21 11:24:24 -04:00

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Systemverilog

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module m #(parameter int Foo);
endmodule
module t (/*AUTOARG*/);
m foo();
endmodule