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4e71f359bf
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com> Co-authored-by: Ryszard Rozak <rrozak@antmicro.com>
123 lines
2.9 KiB
Systemverilog
123 lines
2.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2010-2023 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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`ifdef USE_VPI_NOT_DPI
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//We call it via $c so we can verify DPI isn't required - see bug572
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`else
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import "DPI-C" context function int mon_check();
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`endif
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module \t.has.dots (/*AUTOARG*/
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// Outputs
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\escaped_normal , double__underscore, \9num , \bra[ket]slash/dash-colon:9backslash\done , \x.y ,
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// Inputs
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clk, \b.c , a
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);
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`ifdef VERILATOR
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`systemc_header
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extern "C" int mon_check();
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`verilog
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`endif
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input clk;
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input [7:0] a;
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input \b.c ;
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integer cyc; initial cyc=1;
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output \escaped_normal ;
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wire \escaped_normal = cyc[0];
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output double__underscore ;
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wire double__underscore = cyc[0];
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// C doesn't allow leading non-alpha, so must escape
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output \9num ;
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wire \9num = cyc[0];
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output \bra[ket]slash/dash-colon:9backslash\done ;
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wire \bra[ket]slash/dash-colon:9backslash\done = cyc[0];
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output \x.y ;
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wire \x.y = cyc[0];
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wire \wire = cyc[0];
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wire \check_alias = cyc[0];
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wire \check:alias = cyc[0];
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wire \check;alias = !cyc[0];
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// These are *different entities*, bug83
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wire [31:0] \a0.cyc = ~a0.cyc;
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wire [31:0] \other.cyc = ~a0.cyc;
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integer status;
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sub a0 (.cyc(cyc));
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sub \mod.with_dot (.cyc(cyc));
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// Check if scope names are not decoded twice
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sub ___0F_ (.cyc(cyc));
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sub ___0_ (.cyc(cyc));
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initial begin
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`ifdef VERILATOR
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status = $c32("mon_check()");
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`endif
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`ifdef IVERILOG
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status = $mon_check();
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`endif
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`ifndef USE_VPI_NOT_DPI
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status = mon_check();
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`endif
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if (status != 0) begin
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$write("%%Error: C Test failed with %0d error(s)\n", status);
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$stop;
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end
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$write("%%Info: Checking results\n");
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end
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (escaped_normal != cyc[0]) $stop;
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if (\escaped_normal != cyc[0]) $stop;
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if (double__underscore != cyc[0]) $stop;
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if (\9num != cyc[0]) $stop;
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if (\bra[ket]slash/dash-colon:9backslash\done != cyc[0]) $stop;
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if (\x.y != cyc[0]) $stop;
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if (\wire != cyc[0]) $stop;
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if (\check_alias != cyc[0]) $stop;
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if (\check:alias != cyc[0]) $stop;
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if (\check;alias != !cyc[0]) $stop;
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if (\a0.cyc != ~cyc) $stop;
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if (\other.cyc != ~cyc) $stop;
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if (cyc==10) begin
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if (a != 2) $stop;
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if (\b.c != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub (
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input [31:0] cyc
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);
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reg \b.c ;
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reg subsig1;
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reg subsig2;
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`ifdef IVERILOG
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// stop icarus optimizing signals away
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wire redundant = subsig1 | subsig2 | \b.c ;
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`endif
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endmodule
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