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29 lines
941 B
Python
Executable File
29 lines
941 B
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(
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# Access is so we can dump waves
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v_flags2=['-trace' if test.vlt_all else ' +access+rwc'])
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test.execute()
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if test.vlt_all:
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test.file_grep(test.trace_filename, r'\$enddefinitions')
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sigre = re.escape("bra[ket]slash/dash-colon:9")
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test.file_grep(test.trace_filename, sigre)
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test.file_grep(test.trace_filename, r' other\.cyc ')
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test.file_grep(test.trace_filename, r' module mod\.with_dot ')
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test.vcd_identical(test.trace_filename, test.golden_filename)
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test.passes()
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