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19 lines
439 B
Systemverilog
19 lines
439 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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Cls f;
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rand int r;
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endclass
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module t (/*AUTOARG*/);
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Cls x = new;
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int i;
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initial $display(
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x.f.randomize(),
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x.f.randomize() with { r < 5; },
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i.randomize() with { v < 5; });
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endmodule
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