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46 lines
1018 B
Systemverilog
46 lines
1018 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t (/*AUTOARG*/);
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typedef struct {
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int b[$];
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} st_t;
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typedef struct {
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int v;
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} st_in_t;
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function automatic st_t bar();
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// verilator no_inline_task
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for (int i = 0; i < 4; ++i) begin
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bar.b.push_back(i);
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end
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endfunction // bar
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st_t res;
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st_in_t q[$];
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initial begin
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res = bar();
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`checkd(res.b[0], 0);
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`checkd(res.b[1], 1);
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`checkd(res.b[2], 2);
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`checkd(res.b[3], 3);
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q.push_back(st_in_t'{15});
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q[0].v++;
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`checkd(q[0].v, 16);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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