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23 lines
480 B
Systemverilog
23 lines
480 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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logic [63:0] array = 64'hfeedf00d12345678;
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initial begin
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case ($c("1"))
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1: $stop;
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2: $stop;
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3: $stop;
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default: $stop;
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endcase
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$display("0x%8x", array[$c(0) +: 32]);
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end
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endmodule
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