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50 lines
1.0 KiB
Systemverilog
50 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define N 3
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class Cls;
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task runforks(integer n);
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for (integer i = 0; i < n; i++) fork
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#1 $stop;
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join_none
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endtask
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endclass
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module t;
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Cls cls = new;
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initial begin
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// run forks
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for (integer i = 0; i < `N; i++) fork
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#1 $stop;
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join_none
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// run forks inside a method
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cls.runforks(`N);
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// run forks in forks
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for (integer i = 0; i < `N; i++) fork
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for (integer j = 0; j < `N; j++) fork
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#1 $stop;
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join_none
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join_none
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for (integer i = 0; i < `N; i++) fork
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cls.runforks(`N);
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join_none
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// kill them all
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disable fork;
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// check if we can still fork
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fork
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#2 $write("*-* All Finished *-*\n");
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#3 $finish;
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join_none
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end
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endmodule
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