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12 lines
380 B
Plaintext
12 lines
380 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Stefan Wallentowitz.
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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coverage_block_off -file "t/t_cover_line.v" -lines 141
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coverage_block_off -file "t/t_cover_line.v" -lines 175
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coverage_block_off -module "beta" -block "block"
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