verilator/test_regress/t/t_trace_complex_params_fst.out
Sergi Granell a5aa0e2b0a Add GTKWave FST native tracing, bug1356.
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
2018-10-02 18:42:53 -04:00

206 lines
3.2 KiB
Plaintext

$date
Tue Oct 2 18:35:13 2018
$end
$version
fstWriter
$end
$timescale
1ns
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var wire 32 " cyc $end
$var wire 2 # v_strp $end
$var wire 4 $ v_strp_strp $end
$var wire 2 % v_unip_strp $end
$var wire 2 & v_arrp $end
$var wire 4 ' v_arrp_arrp $end
$var wire 4 ( v_arrp_strp $end
$var wire 1 ) v_arru(1) $end
$var wire 1 * v_arru(2) $end
$var wire 1 + v_arru_arru(3)(1) $end
$var wire 1 , v_arru_arru(3)(2) $end
$var wire 1 - v_arru_arru(4)(1) $end
$var wire 1 . v_arru_arru(4)(2) $end
$var wire 2 / v_arru_arrp(3) $end
$var wire 2 0 v_arru_arrp(4) $end
$var wire 2 1 v_arru_strp(3) $end
$var wire 2 2 v_arru_strp(4) $end
$var real 64 3 v_real $end
$var real 64 4 v_arr_real(0) $end
$var real 64 5 v_arr_real(1) $end
$var wire 64 6 v_str32x2 $end
$scope module unnamedblk1 $end
$var wire 32 7 b $end
$scope module unnamedblk2 $end
$var wire 32 8 a $end
$upscope $end
$upscope $end
$scope module p2 $end
$var wire 32 9 PARAM $end
$upscope $end
$scope module p3 $end
$var wire 32 : PARAM $end
$upscope $end
$upscope $end
$scope module $unit $end
$var wire 1 ; global_bit $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
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b0000000000000000000000000000000100000000000000000000000011111110 6
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b00000000000000000000000000000101 7
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b0000000000000000000000000000011000000000000000000000000011111001 6
b00000000000000000000000000000101 7
b00000000000000000000000000000101 8