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51 lines
1.3 KiB
Systemverilog
51 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define check_rand(cl, field, cond) \
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begin \
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longint prev_result; \
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int ok = 0; \
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for (int i = 0; i < 10; i++) begin \
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longint result; \
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if (!bit'(cl.randomize())) $stop; \
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result = longint'(field); \
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if (!(cond)) $stop; \
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if (i > 0 && result != prev_result) ok = 1; \
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prev_result = result; \
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end \
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if (ok != 1) $stop; \
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end
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class Foo;
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rand int m_intQueue[$];
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rand int m_idx;
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function new;
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m_intQueue = '{10{0}};
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endfunction
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constraint int_queue_c {
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m_idx inside {[0:9]};
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m_intQueue[m_idx] == m_idx + 1;
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foreach (m_intQueue[i]) {
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m_intQueue[i] inside {[0:127]};
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}
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}
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endclass
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module t_randomize_queue_constraints;
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initial begin
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Foo foo = new;
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`check_rand(foo, foo.m_idx, foo.m_idx inside {[0:9]} && foo.m_intQueue[foo.m_idx] == foo.m_idx + 1);
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$display("Queue: %p", foo.m_intQueue);
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`check_rand(foo, foo.m_intQueue[3], foo.m_intQueue[5] inside {[0:127]});
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$display("Queue: %p", foo.m_intQueue);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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