mirror of
https://github.com/verilator/verilator.git
synced 2025-04-15 00:56:56 +00:00
11da07d3b9
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com> Signed-off-by: Ryszard Rozak <rrozak@antmicro.com> Co-authored-by: Ryszard Rozak <rrozak@antmicro.com> Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>
7 lines
558 B
Plaintext
7 lines
558 B
Plaintext
[0] %Error: t_assert_ctl_immediate.v:47: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
|
|
-Info: t/t_assert_ctl_immediate.v:47: Verilog $stop, ignored due to +verilator+error+limit
|
|
[0] %Error: t_assert_ctl_immediate.v:53: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
|
|
[0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed.
|
|
[0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed.
|
|
*-* All Finished *-*
|