verilator/ex_MULTIDRIVEN_msg.rst at a3b255b05405251087fdea7995767acd37ec9b89 - verilator - Gitea: Git with a cup of tea

github/verilator

mirror of https://github.com/verilator/verilator.git synced 2025-01-04 05:37:48 +00:00

Geza Lore 3f89bdcfac

Defer conversion of set flag based AssignDlys (#5091 )

No functional change. Postpone the conversion of all AstAssignDlys that
use the 'VdlySet' scheme for array LHSs until after the complete
traversal of the netlist. The next patch takes advantage of this by
using some extra information also gathered through the traversal to
change the conversion.

AstAssignDlys inside suspendable or fork are not deferred and are
processed identical to the previous version.

There are some TODOs in this patch that are fixed in the next patch.

Output code perturbed due to variable ordering.

MULTIDRIVEN message ordering perturbed due to processing order change.

2024-05-02 00:24:00 +01:00

7 lines

323 B

ReStructuredText

Raw Blame History

 .. comment: generated by t_lint_multidriven_bad
 .. code-block::
    %Warning-MULTIDRIVEN: example.v:1:22 Signal has multiple driving blocks with different clocking: 't.mem'
                          example.v:1:7 ... Location of first driving block
                          example.v:1:7 ... Location of other driving block