verilator/docs/gen/ex_PINMISSING_faulty.rst
2024-07-20 17:50:14 -04:00

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.. comment: generated by t_lint_pinmissing_bad
.. code-block:: sv
:linenos:
:emphasize-lines: 2
module t;
sub sub(); // <--- Warning
endmodule
module sub
(output port);
endmodule