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136 lines
3.4 KiB
Systemverilog
136 lines
3.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Large test for SystemVerilog
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012.
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// SPDX-License-Identifier: CC0-1.0
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// Contributed by M W Lund, Atmel Corporation.
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// *****************************************************************************
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// Top level of System Verilog evalution (Full chip level)
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// *****************************************************************************
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module chip
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#( parameter
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NUMPADS = $size( pinout )
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)
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(
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// **** Pinout ****
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`ifdef VERILATOR // see t_tri_array
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inout wire [NUMPADS:1] pad,
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`else
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inout wire pad [1:NUMPADS],
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`endif
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// **** Inputs !!!! ****
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input logic clk,
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input logic rst
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);
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// ***************************************************************************
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// Local Parameters
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// ***************************************************************************
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localparam
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NSLAVES = 2;
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// ***************************************************************************
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// PADS
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// ***************************************************************************
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// **** Interface ****
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pads_if
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padsif();
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// **** Pad Instansiations ****
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pads
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// #( )
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i_pads
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(
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/*AUTOINST*/
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// Interfaces
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.padsif (padsif.mp_pads),
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// Inouts
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.pad (pad),
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// Inputs
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.clk (clk),
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.rst (rst));
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// ***************************************************************************
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// "dbus" Interface
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// ***************************************************************************
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genbus_if
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#( .NSLAVES(NSLAVES) )
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dbus( .clk(clk), .rst(rst), .test_mode(1'b0) );
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adrdec
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// #( )
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i_adrdec
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(
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/*AUTOINST*/
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// Interfaces
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.dbus (dbus.adrdec));
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// ***************************************************************************
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// CPU ("dbus" Master)
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// ***************************************************************************
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cpu
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#( .ID(1) )
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i_cpu
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(
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/*AUTOINST*/
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// Interfaces
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.dbus (dbus.master),
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// Inputs
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.clk (clk),
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.rst (rst));
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// ***************************************************************************
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// PORTS ("dbus" Slave #1)
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// ***************************************************************************
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ports
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#( .ID(1) )
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i_ports
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(
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/*AUTOINST*/
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// Interfaces
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.dbus (dbus.slave),
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.padsif (padsif.mp_dig),
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// Inputs
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.clk (clk),
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.rst (rst));
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// ***************************************************************************
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// Analog Comparator ("dbus" Slave #2)
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// ***************************************************************************
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ac
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#( .ID(2) )
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i_ac
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(
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/*AUTOINST*/
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// Interfaces
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.dbus (dbus.slave),
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.padsif (padsif.mp_ana),
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// Inputs
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.clk (clk),
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.rst (rst));
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endmodule // chip
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