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72 lines
2.2 KiB
Systemverilog
72 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Large test for SystemVerilog
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012.
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// SPDX-License-Identifier: CC0-1.0
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// Contributed by M W Lund, Atmel Corporation.
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module ac
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#( parameter
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ID = 1 )
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(
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// ***************************************************************************
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// Module Interface (interfaces, outputs, and inputs)
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// ***************************************************************************
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// **** Interfaces ****
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genbus_if.slave dbus,
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pads_if.mp_ana padsif,
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// - System -
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input logic clk,
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input logic rst
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);
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// ***************************************************************************
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// Regs and Wires, Automatics
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// ***************************************************************************
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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logic acenable; // From i_ac_dig of ac_dig.v
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logic acout; // From i_ac_ana of ac_ana.v
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// End of automatics
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// ***************************************************************************
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// Digital Control
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// ***************************************************************************
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ac_dig
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#( .ID(ID) )
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i_ac_dig
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(
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.dbus (dbus),
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/*AUTOINST*/
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// Outputs
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.acenable (acenable),
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// Inputs
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.acout (acout),
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.clk (clk),
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.rst (rst));
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// ***************************************************************************
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// Analog Model
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// ***************************************************************************
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ac_ana
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i_ac_ana
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(
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.padsif (padsif),
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/*AUTOINST*/
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// Outputs
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.acout (acout),
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// Inputs
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.acenable (acenable),
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.clk (clk),
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.rst (rst));
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endmodule // ac
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