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39 lines
964 B
Systemverilog
39 lines
964 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Outputs
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num_zeros, num_ones,
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// Inputs
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clk, reset_l, vec
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);
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input logic clk;
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input logic reset_l;
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input logic [7:0] vec;
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output logic [7:0] num_zeros;
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output logic [7:0] num_ones;
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always_comb begin
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num_zeros = '0;
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num_ones = '0;
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for (int i = 0; i < 8; i++) begin
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if (vec[i] == 0) begin
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num_zeros++;
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end else begin
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num_ones++;
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end
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end
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end
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assert property (@(negedge clk) disable iff (~reset_l) (num_ones == $countones(vec)));
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assert property (@(negedge clk) disable iff (~reset_l) (num_zeros == $countbits(vec, '0)));
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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