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68 lines
1.8 KiB
Systemverilog
68 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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// USING THIS FOR DEBUGGING PROCESS PROPAGATION:
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//
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// The example contains most cases that were problematic during the
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// works on support of 'disable fork' statement, including:
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//
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// - indirect use of disable fork (through a task),
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// - indirect use of forks that are to be disabled,
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// - forks in forks,
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// - a function taking VlProcess argument shared between a process that
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// allocates VlProcess, and one that doesnt,
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// - a function that has a delay and obtains VlProcess argument,
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// - a function that has a delay and doesn't obtain it,
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// - an empty fork with disable fork.
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//
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// Blocks below contain info on whether they should (YES) or shouldn't (NO)
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// be emitted as functions with a VlProcess argument.
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//
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// To check if that corresponds to reality, see blue nodes in proc_deps.dot
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class Cls;
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task print; /*NO*/
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$write("*-* All ");
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endtask
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task disable_fork_func; /*YES*/
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disable fork;
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endtask
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task common_func; /*YES*/
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fork /*YES*/ #1; join_none
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endtask
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task fork_func; /*YES*/
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fork /*YES*/ #1 $stop; join_none
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endtask
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task delay_func; /*NO*/
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fork /*NO*/ #1 $write("Finished *-*\n"); join_none
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endtask
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task empty_fork;
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fork
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begin
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end
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join_none
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disable fork;
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endtask
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endclass
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module t;
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Cls cls = new;
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initial begin /*YES*/
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fork /*YES*/ cls.common_func(); join_none
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cls.fork_func();
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cls.disable_fork_func();
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cls.empty_fork();
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cls.print();
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end
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initial begin /*NO*/
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cls.delay_func();
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cls.common_func();
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fork /*YES*/ disable fork; join_none
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end
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endmodule
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