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27 lines
544 B
Systemverilog
27 lines
544 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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virtual class Base;
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pure constraint raint;
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endclass
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class Cls extends Base;
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rand int b2;
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constraint raint { b2 == 5; }
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endclass
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virtual class Virt extends Base;
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// No constraint needed
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endclass
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module t;
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initial begin
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Cls c = new;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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