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26 lines
469 B
Systemverilog
26 lines
469 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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wire sig;
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foo foo(sig);
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initial #1 begin
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$write("*-* All Finished *-*\n");
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$finish();
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end
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endmodule
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module foo(inout sig);
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reg cond = $c(0);
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always @(sig) begin
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if (cond) begin
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#1; $c("");
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end
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end
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endmodule
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