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https://github.com/verilator/verilator.git
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139 lines
4.2 KiB
Systemverilog
139 lines
4.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);
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typedef enum bit [5:0] {
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A = 6'b111000,
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B = 6,b111111
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} enum_t;
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module t (/*AUTOARG*/);
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initial begin
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bit arr[];
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bit [1:0] arr2[$];
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bit [5:0] arr6[$];
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bit [5:0] bit6 = 6'b111000;
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bit [5:0] ans;
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bit [3:0] arr4[] = '{25{4'b1000}};
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bit [7:0] arr8[] = '{8{8'b00110011}};
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bit [63:0] arr64[] = '{5{64'h0123456789abcdef}};
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bit [159:0] arr160[] = '{2{160'h0123456789abcdef0123456789abcdef01234567}};
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bit [63:0] bit64;
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bit [99:0] bit100;
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bit [319:0] bit320;
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enum_t ans_enum;
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{ >> bit {arr}} = bit6;
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`checkp(arr, "'{'h0, 'h0, 'h0, 'h1, 'h1, 'h1} ");
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ans = { >> bit {arr} };
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`checkh(ans, bit6);
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ans_enum = enum_t'({ >> bit {arr} });
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`checkh(ans_enum, bit6);
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{ << bit {arr}} = bit6;
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`checkp(arr, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0} ");
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ans = { << bit {arr} };
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`checkh(ans, bit6);
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ans_enum = enum_t'({ << bit {arr} });
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`checkh(ans_enum, bit6);
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{ >> bit[1:0] {arr2}} = bit6;
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`checkp(arr2, "'{'h0, 'h2, 'h3} ");
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ans = { >> bit[1:0] {arr2} };
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`checkh(ans, bit6);
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ans_enum = enum_t'({ >> bit[1:0] {arr2} });
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`checkh(ans_enum, bit6);
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{ << bit[1:0] {arr2}} = bit6;
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`checkp(arr2, "'{'h3, 'h2, 'h0} ");
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ans = { << bit[1:0] {arr2} };
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`checkh(ans, bit6);
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ans_enum = enum_t'({ << bit[1:0] {arr2} });
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`checkh(ans_enum, bit6);
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{ >> bit [5:0] {arr6} } = bit6;
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`checkp(arr6, "'{'h38} ");
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ans = { >> bit[5:0] {arr6} };
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`checkh(ans, bit6);
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ans_enum = enum_t'({ >> bit[5:0] {arr6} });
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`checkh(ans_enum, bit6);
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{ << bit [5:0] {arr6} } = bit6;
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`checkp(arr6, "'{'h38} ");
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ans = { << bit[5:0] {arr6} };
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`checkh(ans, bit6);
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ans_enum = enum_t'({ << bit[5:0] {arr6} });
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`checkh(ans_enum, bit6);
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bit64 = { >> bit {arr8} };
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`checkh(bit64[7:0], 8'b00110011);
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bit64 = { << bit {arr8} };
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`checkh(bit64[7:0], 8'b11001100);
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{ >> bit {arr8} } = bit64;
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`checkh(arr8[0], 8'b11001100);
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{ << bit {arr8} } = bit64;
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`checkh(arr8[0], 8'b00110011);
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bit100 = { >> bit {arr4} };
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`checkh(bit100[3:0], 4'b1000);
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bit100 = { << bit {arr4} };
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`checkh(bit100[3:0], 4'b0001);
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{ >> bit {arr4} } = bit100;
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`checkh(arr4[0], 4'b0001);
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{ << bit {arr4} } = bit100;
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`checkh(arr4[0], 4'b1000);
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bit320 = { >> byte {arr64} };
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`checkh(bit320[63:0], 64'h0123456789abcdef);
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bit320 = { << byte {arr64} };
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`checkh(bit320[63:0], 64'hefcdab8967452301);
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{ >> byte {arr64} } = bit320;
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`checkh(arr64[0], 64'hefcdab8967452301);
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{ << byte {arr64} } = bit320;
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`checkh(arr64[0], 64'h0123456789abcdef);
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{ >> bit {arr64} } = bit64;
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`checkh(arr64[0], 64'hcccccccccccccccc);
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{ << bit {arr64} } = bit64;
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`checkh(arr64[0], 64'h3333333333333333);
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bit64 = { >> bit {arr64} };
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`checkh(bit64, 64'h3333333333333333);
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bit64 = { << bit {arr64} };
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`checkh(bit64, 64'hcccccccccccccccc);
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bit320 = { >> byte {arr160} };
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`checkh(bit320[159:0], 160'h0123456789abcdef0123456789abcdef01234567);
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bit320 = { << byte {arr160} };
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`checkh(bit320[159:0], 160'h67452301efcdab8967452301efcdab8967452301);
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{ >> byte {arr160} } = bit320;
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`checkh(arr160[0], 160'h67452301efcdab8967452301efcdab8967452301);
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{ << byte {arr160} } = bit320;
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`checkh(arr160[0], 160'h0123456789abcdef0123456789abcdef01234567);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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