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124 lines
3.9 KiB
Verilog
124 lines
3.9 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
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`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
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module t (/*AUTOARG*/);
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bit fail;
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reg signed [3:0] w4_s;
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reg signed [4:0] w5_s;
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reg [2:0] w3_u;
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reg [3:0] w4_u;
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reg [4:0] w5_u;
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real r;
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reg signed [4:0] bug754_a;
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integer i;
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//verilator lint_off WIDTH
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wire a = (5'b0 == (5'sb11111 >>> 3'd7));
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wire b = (5'sb11111 == (5'sb11111 >>> 3'd7));
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wire c = (1'b0+(5'sb11111 >>> 3'd7));
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wire d = (1'sb0+(5'sb11111 >>> 3'd7));
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wire e = (5'b0 == (5'sb11111 / 5'sd3));
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wire f = (5'sb0 == (5'sb11111 / 5'sd3));
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wire g = (5'b01010 == (5'b11111 / 5'sd3));
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initial begin
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// verilator lint_off STMTDLY
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#1;
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`ifdef VCS // I-2014.03
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`checkh({a, b, c, d, e, f, g}, 7'b1101111);
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`else
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`checkh({a, b, c, d, e, f, g}, 7'b1101011);
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`endif
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//======================================================================
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if ((-1 >>> 3) != -1) $stop; // Decimals are signed
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i = 3'sb111 >>> 3;
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`checkh(i, -1);
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i = -1 >>> 3;
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`checkh(i, -1);
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bug754_a = -1;
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w4_u = |0 != (bug754_a >>> 3'd7);
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`checkh(w4_u, 4'b0);
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// Sanity check: -1>>7 == -1
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w5_u = (5'sb11111 >>> 3'd7);
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`checkh(w5_u, 5'b11111);
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// bug756
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w4_u = (5'b0 == (5'sb11111 >>> 3'd7));
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`checkh(w4_u, 4'b0001);
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w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); // Exp 0 Vlt 0
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`checkh(w4_u, 4'b0001);
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w4_u = ((5'b01111 == (5'sb11111 / 5'sd2))); // Strength-reduces to >>>
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`ifdef VCS // I-2014.03
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`checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate
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`else
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`checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ...
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`endif
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// Does == sign propagate from lhs to rhs? Yes, but not in VCS
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w4_u = ((5'b01010 == (5'sb11111 / 5'sd3))); // Exp 0 Vlt 0 // Must be signed result (-1/3) to make this result zero
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`ifdef VCS // I-2014.03
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`checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate
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`else
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`checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ...
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`endif
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w4_u = (1'b0+(5'sb11111 >>> 3'd7)); // Exp 00000 Vlt 000000 Actually the signedness of result does NOT matter
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`checkh(w4_u, 4'b0000);
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w4_u = (5'sb0 == (5'sb11111 / 5'sd3)); // Must be signed result (-1/3) to make this result zero
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`checkh(w4_u, 4'b0001);
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// Does == width propagate from lhs to rhs? Yes
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w4_u = (3'b100==(3'b111 << 2));
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`checkh(w4_u, 4'b0001);
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w4_u = (4'b100==(3'b111 << 2));
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`checkh(w4_u, 4'b0000);
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w4_u = (4'b1100==(3'b111 << 2));
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`checkh(w4_u, 4'b0001);
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// Does >>> sign propagate from input same as for +? Yes
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w4_u = (1'b0+(5'sb11111 >>> 3'd7));
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`checkh(w4_u, 4'b0000);
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w4_u = (1'sb0+(5'sb11111 >>> 3'd7));
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`checkh(w4_u, 4'b1111);
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// Does << width propagate from input same as for +? Yes
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w4_u = (3'b0+(3'b111 << 2));
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`checkh(w4_u, 4'b1100); // width 4 =='s LHS
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w4_u = (4'b0+(3'b111 << 2));
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`checkh(w4_u, 4'b1100);
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w4_u = (5'sb11111 == (5'sb11111 >>> 3'd7)); // WHAT? Signedness does propagate across ==?????
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`checkh(w4_u, 4'b0001);
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w4_u = ((5'b0 == (5'sb11111 >>> 3'd7)));
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`checkh(w4_u, 4'b0001);
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// bug756
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w5_s = -1;
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w3_u = 7;
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w4_u = |0 != (w5_s >>> w3_u);
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`checkh(w4_u, 4'b0000);
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// bug763
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w3_u = 2;
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w4_u = (w3_u >> 2'b11) >> 1;
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`checkh(w4_u, 4'b0000);
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if (fail) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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