mirror of
https://github.com/verilator/verilator.git
synced 2025-01-09 16:17:36 +00:00
acf4a3fa99
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
312 lines
3.0 KiB
Plaintext
312 lines
3.0 KiB
Plaintext
$date
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Tue Aug 28 15:07:10 2018
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$end
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$version
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lxt2vcd
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$end
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$timescale 1ns $end
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$scope module top $end
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$scope module $unit $end
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$var wire 1 ! global_bit $end
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$upscope $end
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$var wire 1 " clk $end
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$scope module t $end
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$var wire 32 # cyc [31:0] $end
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$scope module unnamedblk1 $end
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$var wire 32 $ b [31:0] $end
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$scope module unnamedblk2 $end
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$var wire 32 % a [31:0] $end
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$upscope $end
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$upscope $end
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$var real 1 & v_arr_real(0) $end
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$var real 1 ' v_arr_real(1) $end
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$var wire 2 ( v_arrp [2:1] $end
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$var wire 2 ) v_arrp_arrp(3) [1:0] $end
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$var wire 2 * v_arrp_arrp(4) [1:0] $end
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$scope module v_arrp_strp(3) $end
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$var wire 1 + b0 $end
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$var wire 1 , b1 $end
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$upscope $end
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$scope module v_arrp_strp(4) $end
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$var wire 1 - b0 $end
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$var wire 1 . b1 $end
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$upscope $end
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$var wire 1 / v_arru(1) $end
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$var wire 1 0 v_arru(2) $end
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$var wire 2 1 v_arru_arrp(3) [2:1] $end
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$var wire 2 2 v_arru_arrp(4) [2:1] $end
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$var wire 1 3 v_arru_arru(3)(1) $end
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$var wire 1 4 v_arru_arru(3)(2) $end
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$var wire 1 5 v_arru_arru(4)(1) $end
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$var wire 1 6 v_arru_arru(4)(2) $end
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$scope module v_arru_strp(3) $end
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$var wire 1 7 b0 $end
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$var wire 1 8 b1 $end
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$upscope $end
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$scope module v_arru_strp(4) $end
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$var wire 1 9 b0 $end
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$var wire 1 : b1 $end
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$upscope $end
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$var real 1 ; v_real $end
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$scope module v_str32x2(0) $end
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$var wire 32 < data [31:0] $end
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$upscope $end
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$scope module v_str32x2(1) $end
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$var wire 32 = data [31:0] $end
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$upscope $end
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$scope module v_strp $end
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$var wire 1 > b0 $end
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$var wire 1 ? b1 $end
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$upscope $end
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$scope module v_strp_strp $end
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$scope module x0 $end
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$var wire 1 @ b0 $end
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$var wire 1 A b1 $end
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$upscope $end
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$scope module x1 $end
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$var wire 1 B b0 $end
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$var wire 1 C b1 $end
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$upscope $end
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$upscope $end
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$scope module v_unip_strp $end
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$scope module x1 $end
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$var wire 1 D b0 $end
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$var wire 1 E b1 $end
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$upscope $end
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$upscope $end
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$var wire 1 " clk $end
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$scope module v_unip_strp $end
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$scope module x0 $end
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$var wire 1 D b0 $end
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$var wire 1 E b1 $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$dumpvars
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#0
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1!
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0"
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b0 #
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b0 $
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b0 %
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r0 &
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r0 '
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b0 (
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b0 )
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b0 *
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0+
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0,
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0-
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0.
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0/
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00
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b0 1
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b0 2
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03
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04
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05
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06
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07
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08
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09
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0:
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r0 ;
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b11111111 <
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b0 =
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0>
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0?
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0@
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0A
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0B
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0C
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0D
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0E
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#10
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1E
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1D
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1C
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1B
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1A
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1@
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1?
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1>
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b1 =
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b11111110 <
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r0.1 ;
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1:
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19
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18
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17
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b11 2
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b11 1
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1.
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1-
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1,
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1+
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b11 *
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b11 )
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b11 (
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r0.3 '
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r0.2 &
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b101 %
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b101 $
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b1 #
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1"
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#15
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0"
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#20
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1"
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b10 #
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r0.4 &
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r0.6 '
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b0 (
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b0 )
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b0 *
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0+
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0,
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0-
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0.
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b0 1
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b0 2
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07
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08
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09
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0:
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r0.2 ;
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b11111101 <
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b10 =
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0>
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0?
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0@
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0A
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0B
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0C
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0D
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0E
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#25
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0"
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#30
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1"
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1E
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1D
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1C
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1B
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1A
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1@
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1?
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1>
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b11 =
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b11111100 <
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r0.3 ;
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1:
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19
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18
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17
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b11 2
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b11 1
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1.
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1-
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1,
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1+
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b11 *
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b11 )
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b11 (
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r0.8999999999999999 '
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r0.6000000000000001 &
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b11 #
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#35
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0"
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#40
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1"
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b100 #
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r0.8 &
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r1.2 '
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b0 (
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b0 )
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b0 *
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0+
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0,
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0-
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0.
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b0 1
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b0 2
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07
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08
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09
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0:
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r0.4 ;
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b11111011 <
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b100 =
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0>
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0?
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0@
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0A
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0B
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0C
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0D
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0E
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#45
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0"
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#50
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1"
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1E
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1D
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1C
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1B
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1A
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1@
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1?
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1>
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b101 =
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b11111010 <
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r0.5 ;
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1:
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19
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18
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17
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b11 2
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b11 1
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1.
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1-
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1,
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1+
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b11 *
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b11 )
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b11 (
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r1.5 '
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r1 &
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b101 #
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#55
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0"
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#60
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1"
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b110 #
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r1.2 &
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r1.8 '
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b0 (
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b0 )
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b0 *
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0+
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0,
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0-
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0.
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b0 1
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b0 2
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07
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08
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09
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0:
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r0.6 ;
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b11111001 <
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b110 =
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0>
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0?
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0@
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0A
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0B
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0C
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0D
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0E
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