mirror of
https://github.com/verilator/verilator.git
synced 2025-01-09 16:17:36 +00:00
194 lines
2.3 KiB
Plaintext
194 lines
2.3 KiB
Plaintext
$date
|
|
Tue Aug 28 15:03:55 2018
|
|
$end
|
|
$version
|
|
lxt2vcd
|
|
$end
|
|
$timescale 1ns $end
|
|
$scope module top $end
|
|
$scope module $unit $end
|
|
$var wire 1 ! global_bit $end
|
|
$upscope $end
|
|
$var wire 1 " clk $end
|
|
$scope module t $end
|
|
$var wire 32 # cyc [31:0] $end
|
|
$scope module p2 $end
|
|
$var wire 32 $ PARAM [31:0] $end
|
|
$upscope $end
|
|
$scope module p3 $end
|
|
$var wire 32 % PARAM [31:0] $end
|
|
$upscope $end
|
|
$scope module unnamedblk1 $end
|
|
$var wire 32 & b [31:0] $end
|
|
$scope module unnamedblk2 $end
|
|
$var wire 32 ' a [31:0] $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$var real 1 ( v_arr_real(0) $end
|
|
$var real 1 ) v_arr_real(1) $end
|
|
$var wire 2 * v_arrp [2:1] $end
|
|
$var wire 4 + v_arrp_arrp [3:0] $end
|
|
$var wire 4 , v_arrp_strp [3:0] $end
|
|
$var wire 1 - v_arru(1) $end
|
|
$var wire 1 . v_arru(2) $end
|
|
$var wire 2 / v_arru_arrp(3) [2:1] $end
|
|
$var wire 2 0 v_arru_arrp(4) [2:1] $end
|
|
$var wire 1 1 v_arru_arru(3)(1) $end
|
|
$var wire 1 2 v_arru_arru(3)(2) $end
|
|
$var wire 1 3 v_arru_arru(4)(1) $end
|
|
$var wire 1 4 v_arru_arru(4)(2) $end
|
|
$var wire 2 5 v_arru_strp(3) [1:0] $end
|
|
$var wire 2 6 v_arru_strp(4) [1:0] $end
|
|
$var real 1 7 v_real $end
|
|
$var wire 64 8 v_str32x2 [63:0] $end
|
|
$var wire 2 9 v_strp [1:0] $end
|
|
$var wire 4 : v_strp_strp [3:0] $end
|
|
$var wire 2 ; v_unip_strp [1:0] $end
|
|
$var wire 1 " clk $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$enddefinitions $end
|
|
$dumpvars
|
|
#0
|
|
1!
|
|
0"
|
|
b0 #
|
|
b10 $
|
|
b11 %
|
|
b0 &
|
|
b0 '
|
|
r0 (
|
|
r0 )
|
|
b0 *
|
|
b0 +
|
|
b0 ,
|
|
0-
|
|
0.
|
|
b0 /
|
|
b0 0
|
|
01
|
|
02
|
|
03
|
|
04
|
|
b0 5
|
|
b0 6
|
|
r0 7
|
|
b11111111 8
|
|
b0 9
|
|
b0 :
|
|
b0 ;
|
|
#10
|
|
b11 ;
|
|
b1111 :
|
|
b11 9
|
|
b100000000000000000000000011111110 8
|
|
r0.1 7
|
|
b11 6
|
|
b11 5
|
|
b11 0
|
|
b11 /
|
|
b1111 ,
|
|
b1111 +
|
|
b11 *
|
|
r0.3 )
|
|
r0.2 (
|
|
b101 '
|
|
b101 &
|
|
b1 #
|
|
1"
|
|
#15
|
|
0"
|
|
#20
|
|
1"
|
|
b10 #
|
|
r0.4 (
|
|
r0.6 )
|
|
b0 *
|
|
b0 +
|
|
b0 ,
|
|
b0 /
|
|
b0 0
|
|
b0 5
|
|
b0 6
|
|
r0.2 7
|
|
b1000000000000000000000000011111101 8
|
|
b0 9
|
|
b0 :
|
|
b0 ;
|
|
#25
|
|
0"
|
|
#30
|
|
1"
|
|
b11 ;
|
|
b1111 :
|
|
b11 9
|
|
b1100000000000000000000000011111100 8
|
|
r0.3 7
|
|
b11 6
|
|
b11 5
|
|
b11 0
|
|
b11 /
|
|
b1111 ,
|
|
b1111 +
|
|
b11 *
|
|
r0.8999999999999999 )
|
|
r0.6000000000000001 (
|
|
b11 #
|
|
#35
|
|
0"
|
|
#40
|
|
1"
|
|
b100 #
|
|
r0.8 (
|
|
r1.2 )
|
|
b0 *
|
|
b0 +
|
|
b0 ,
|
|
b0 /
|
|
b0 0
|
|
b0 5
|
|
b0 6
|
|
r0.4 7
|
|
b10000000000000000000000000011111011 8
|
|
b0 9
|
|
b0 :
|
|
b0 ;
|
|
#45
|
|
0"
|
|
#50
|
|
1"
|
|
b11 ;
|
|
b1111 :
|
|
b11 9
|
|
b10100000000000000000000000011111010 8
|
|
r0.5 7
|
|
b11 6
|
|
b11 5
|
|
b11 0
|
|
b11 /
|
|
b1111 ,
|
|
b1111 +
|
|
b11 *
|
|
r1.5 )
|
|
r1 (
|
|
b101 #
|
|
#55
|
|
0"
|
|
#60
|
|
1"
|
|
b110 #
|
|
r1.2 (
|
|
r1.8 )
|
|
b0 *
|
|
b0 +
|
|
b0 ,
|
|
b0 /
|
|
b0 0
|
|
b0 5
|
|
b0 6
|
|
r0.6 7
|
|
b11000000000000000000000000011111001 8
|
|
b0 9
|
|
b0 :
|
|
b0 ;
|