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34a0bb448e
- Merge AstNodeIf nodes as well (not just assignment from AstCond) - Merge merged results recursively (optimizes nested conditionals/ifs) - Only checking mergeability once per node. - Don't add redundant masking - Duplicate cheap statements in both branches, if doing so yields a larger merge - Include reduced nodes before the starting conditional in the merge
23 lines
661 B
Perl
Executable File
23 lines
661 B
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2019 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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compile(
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verilator_flags2 => ['--stats', "-Ow"],
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);
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if ($Self->{vlt_all}) {
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file_grep($Self->{stats}, qr/Node count, IF +\d+ +\d+ +\d+ +\d+ +(\d+)/, 11);
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}
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ok(1);
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1;
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