mirror of
https://github.com/verilator/verilator.git
synced 2025-02-08 06:32:24 +00:00
7708c88e32
Static variables of functions are created in the function. When blocks in a function use identical names for static variables, we need to name those variables properly.
35 lines
658 B
Systemverilog
35 lines
658 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2020 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t;
|
|
|
|
function do_stuff();
|
|
static int some_int;
|
|
begin: block0
|
|
static int some_int;
|
|
end
|
|
begin: block1
|
|
static int some_int;
|
|
end
|
|
begin
|
|
static int some_int;
|
|
end
|
|
begin: block2
|
|
begin: block3
|
|
static int some_int;
|
|
end
|
|
begin
|
|
static int some_int;
|
|
end
|
|
end
|
|
endfunction
|
|
|
|
initial begin
|
|
$write("*-* All Finished *-*\n");
|
|
$finish();
|
|
end
|
|
|
|
endmodule
|