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53 lines
1.2 KiB
Systemverilog
53 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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process p;
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integer seed;
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string state;
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int a;
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int b;
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initial begin
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p = process::self();
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// Test setting RNG state with state string
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state = p.get_randstate();
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p.set_randstate(state);
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a = $random;
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p.set_randstate(state);
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b = $random;
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$display("a=%d, b=%d", a, b);
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if (a != b) $stop;
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// Test the same with $urandom
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state = p.get_randstate();
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p.set_randstate(state);
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a = $urandom;
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p.set_randstate(state);
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b = $urandom;
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$display("a=%d, b=%d", a, b);
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if (a != b) $stop;
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// Test if the results repeat after the state is reset
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state = p.get_randstate();
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for (int i = 0; i < 10; i++)
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$random;
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a = $random;
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// Now reset the state and take 11th result again
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p.set_randstate(state);
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for (int i = 0; i < 10; i++)
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$random;
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b = $random;
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$display("a=%d, b=%d", a, b);
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if (a != b) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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