verilator/test_regress/t/t_assert_procedural_clk.out
2023-07-02 16:12:09 -04:00

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%Error: t/t_assert_procedural_clk.v:21:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2917 16.14.6)
: ... In instance t
21 | assume property (@(posedge clk) cyc == 9);
| ^~~~~~
%Error: t/t_assert_procedural_clk.v:22:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2917 16.14.6)
: ... In instance t
22 | assume property (@(negedge clk) cyc == 9);
| ^~~~~~
%Error: Exiting due to