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72 lines
1.7 KiB
Verilog
72 lines
1.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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passed,
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// Inputs
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clk, fastclk, reset_l
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);
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input clk /*verilator sc_clock*/;
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input fastclk /*verilator sc_clock*/;
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input reset_l;
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output passed;
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// Combine passed signals from each sub signal
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// verilator lint_off MULTIDRIVEN
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wire [20:0] passedv;
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// verilator lint_on MULTIDRIVEN
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wire passed = &passedv;
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assign passedv[0] = 1'b1;
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assign passedv[1] = 1'b1;
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assign passedv[2] = 1'b1;
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assign passedv[3] = 1'b1;
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assign passedv[4] = 1'b1;
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assign passedv[5] = 1'b1;
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t_inst tinst
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(.passed (passedv[6]),
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/*AUTOINST*/
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// Inputs
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.clk (clk),
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.fastclk (fastclk));
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t_param tparam
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(.passed (passedv[7]),
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/*AUTOINST*/
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// Inputs
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.clk (clk));
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assign passedv[8] = 1'b1;
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assign passedv[9] = 1'b1;
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assign passedv[10] = 1'b1;
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t_clk tclk
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(.passed (passedv[11]),
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/*AUTOINST*/
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// Inputs
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.fastclk (fastclk),
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.clk (clk),
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.reset_l (reset_l));
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assign passedv[12] = 1'b1;
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assign passedv[13] = 1'b1;
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t_chg tchg
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(.passed (passedv[14]),
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/*AUTOINST*/
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// Inputs
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.clk (clk),
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.fastclk (fastclk));
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assign passedv[15] = 1'b1;
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assign passedv[16] = 1'b1;
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assign passedv[17] = 1'b1;
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assign passedv[18] = 1'b1;
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assign passedv[19] = 1'b1;
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t_netlist tnetlist
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(.passed (passedv[20]),
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.also_fastclk (fastclk),
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/*AUTOINST*/
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// Inputs
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.fastclk (fastclk));
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endmodule
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