mirror of
https://github.com/verilator/verilator.git
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95c4ade718
This patch adds some abstract enums to pass to the trace decl* APIs, so
the VCD/FST specific code can be kept in verilated_{vcd,fst}_*.cc, and
removed from V3Emit*. It also reworks the generation of the trace init
functions (those that call 'decl*' for the signals) such that the scope
hierarchy is traversed precisely once during initialization, which
simplifies the FST writer. This later change also has the side effect of
fixing tracing of nested interfaces when traced via an interface
reference - see the change in the expected t_interface_ref_trace - which
previously were missed.
355 lines
5.1 KiB
Plaintext
355 lines
5.1 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$timescale 1ps $end
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$scope module top $end
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$scope module $unit $end
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$var wire 1 # global_bit $end
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$upscope $end
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$var wire 1 I clk $end
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$scope module t $end
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$var wire 1 I clk $end
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$var wire 32 $ cyc [31:0] $end
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$scope module v_strp $end
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$var wire 1 % b1 $end
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$var wire 1 & b0 $end
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$upscope $end
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$scope module v_strp_strp $end
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$scope module x1 $end
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$var wire 1 ' b1 $end
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$var wire 1 ( b0 $end
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$upscope $end
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$scope module x0 $end
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$var wire 1 ) b1 $end
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$var wire 1 * b0 $end
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$upscope $end
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$upscope $end
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$scope module v_unip_strp $end
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$scope module x1 $end
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$var wire 1 + b1 $end
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$var wire 1 , b0 $end
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$upscope $end
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$scope module x0 $end
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$var wire 1 + b1 $end
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$var wire 1 , b0 $end
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$upscope $end
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$upscope $end
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$var wire 2 - v_arrp [2:1] $end
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$var wire 2 . v_arrp_arrp[3] [2:1] $end
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$var wire 2 / v_arrp_arrp[4] [2:1] $end
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$scope module v_arrp_strp[3] $end
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$var wire 1 0 b1 $end
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$var wire 1 1 b0 $end
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$upscope $end
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$scope module v_arrp_strp[4] $end
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$var wire 1 2 b1 $end
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$var wire 1 3 b0 $end
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$upscope $end
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$var wire 1 J v_arru[1] $end
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$var wire 1 K v_arru[2] $end
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$var wire 1 L v_arru_arru[3][1] $end
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$var wire 1 M v_arru_arru[3][2] $end
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$var wire 1 N v_arru_arru[4][1] $end
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$var wire 1 O v_arru_arru[4][2] $end
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$var wire 2 4 v_arru_arrp[3] [2:1] $end
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$var wire 2 5 v_arru_arrp[4] [2:1] $end
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$scope module v_arru_strp[3] $end
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$var wire 1 6 b1 $end
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$var wire 1 7 b0 $end
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$upscope $end
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$scope module v_arru_strp[4] $end
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$var wire 1 8 b1 $end
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$var wire 1 9 b0 $end
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$upscope $end
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$var real 64 : v_real $end
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$var real 64 < v_arr_real[0] $end
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$var real 64 > v_arr_real[1] $end
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$scope module v_str32x2[0] $end
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$var wire 32 @ data [31:0] $end
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$upscope $end
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$scope module v_str32x2[1] $end
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$var wire 32 A data [31:0] $end
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$upscope $end
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$var wire 32 B v_enumed [31:0] $end
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$var wire 32 C v_enumed2 [31:0] $end
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$var wire 3 D v_enumb [2:0] $end
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$scope module v_enumb2_str $end
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$var wire 3 E a [2:0] $end
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$var wire 3 F b [2:0] $end
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$upscope $end
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$var wire 8 P unpacked_array[-2] [7:0] $end
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$var wire 8 Q unpacked_array[-1] [7:0] $end
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$var wire 8 R unpacked_array[0] [7:0] $end
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$var wire 1 S LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
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$scope module unnamedblk1 $end
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$var wire 32 G b [31:0] $end
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$scope module unnamedblk2 $end
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$var wire 32 H a [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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