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43 lines
1.3 KiB
Systemverilog
43 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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static task fork_w_zerodly(longint unsigned current_time);
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bit my_bit;
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bit zero_dly_first = 0;
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// Th code below relies on Verilator's deterministic scheduler and is not
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// compatible across different simulators.
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//
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// The `zero_dly` block is going to be executed first and then suspended at the #0 delay.
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// Then the `finish_before` block is going to be executed. Once that happens, the
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// execution of `zero_dly` block should be resumed, all within a single time-slot.
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//
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// IF THIS TEST FAILS AFTER CHANGES TO VERILATOR'S SCHEDULER, IT DOESN'T NECESSARILY
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// MEAN THE CHANGES ARE WRONG.
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fork
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begin : zero_dly
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zero_dly_first = 1;
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#0;
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if (current_time != $time) $stop;
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if (my_bit == 0) $stop;
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end : zero_dly
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begin : finish_before
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if (!zero_dly_first) $stop;
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my_bit = 1;
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end : finish_before
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join_none
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#1 $display("After fork."); // Check if there's no skipped coroutine
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endtask
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endclass
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module test();
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initial begin
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Foo::fork_w_zerodly($time);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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