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44 lines
837 B
Systemverilog
44 lines
837 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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typedef process pr;
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pr p[4];
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int n = 0;
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initial begin
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wait (p[1]);
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p[1].await();
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p[0] = process::self();
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if (n == 3) n++;
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#2 $write("*-* All Finished *-*\n");
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$finish;
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end
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initial begin
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wait (p[2]);
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p[2].await();
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p[1] = process::self();
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if (n == 2) n++;
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end
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initial begin
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wait (p[3]);
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p[3].await();
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p[2] = process::self();
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if (n == 1) n++;
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end
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initial begin
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p[3] = process::self();
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if (n == 0) n++;
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end
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initial #1 if (n != 4) $stop;
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initial #3 $stop; // timeout
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endmodule
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