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47 lines
1.1 KiB
Systemverilog
47 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Toru Niina.
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// SPDX-License-Identifier: CC0-1.0
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`ifdef TEST_VERBOSE
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`define WRITE_VERBOSE(msg) $write(msg)
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`else
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`define WRITE_VERBOSE(msg)
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`endif
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`default_nettype none
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`timescale 1ns/1ps
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module t;
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localparam cycle = 1000.0 / 100.0;
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localparam halfcycle = 0.5 * cycle;
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logic clk = '0;
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import "DPI-C" context task tb_c_wait();
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export "DPI-C" task tb_sv_wait;
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task automatic tb_sv_wait(input int n);
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`WRITE_VERBOSE("tb_sv_wait start...\n");
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repeat(n) @(negedge clk);
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`WRITE_VERBOSE("tb_sv_wait done!\n");
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endtask
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always #halfcycle clk = ~clk;
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initial begin
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`WRITE_VERBOSE("test start\n");
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repeat(10) @(posedge clk);
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`WRITE_VERBOSE("calling tb_c_wait...\n");
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tb_c_wait();
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`WRITE_VERBOSE("tb_c_wait finish\n");
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repeat(10) @(posedge clk);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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initial #(cycle*30) $stop; // timeout
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endmodule
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