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16 lines
411 B
Systemverilog
16 lines
411 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2017 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t ();
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initial begin
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forever begin end
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// verilator lint_off UNSIGNED
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for (reg [31:0] i=0; i>=0; i=i+1) begin end
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$display; // So loop not eaten
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end
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endmodule
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