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34 lines
758 B
Systemverilog
34 lines
758 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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int x;
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function new;
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x = 10;
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endfunction
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function bit set_x(int a);
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x = a;
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return 1;
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endfunction
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function int get_x;
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return x;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Cls cls;
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if (cls != null && cls.x == 10) $stop;
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if (cls != null && cls.get_x() == 10) $stop;
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cls = new;
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if (!cls.set_x(1) || cls.x != 1) $stop;
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if (!cls.set_x(2) || cls.get_x() != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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